Silicon photonics is rapidly gaining importance as a generic technology platform for a wide range of applications. Such applications include, for instance, telecom, datacom, interconnect and sensing. Silicon photonics allows implementing photonic functions through the use of complementary metal-oxide-semiconductor (CMOS) compatible wafer-scale technologies on high quality, low cost silicon substrates.
However, especially for telecom applications it is difficult to meet all performance requirements, when using conventional silicon passive devices. Instead, it has been found that a dramatically improved performance can be achieved by using high quality silicon nitride (SiN) technology, which is still a CMOS compatible wafer-scale technology. As a drawback, active devices cannot be fabricated using SiN.
One option to overcome this drawback is to monolithically integrate SiN waveguides with active devices fabricated using silicon, i.e. devices formed in silicon waveguides. However, high temperatures are necessary to ensure a high quality of the SiN waveguides. Therefore the silicon active devices must be formed after the SiN has been annealed (and therefore on top of the SiN). This is described in WO 2014/009029 A1. Therein a mono-crystalline silicon layer is wafer bonded above a (planarized) SiN waveguide. Although the number of process steps is comparable to the standard silicon on insulator (SOI) program this approach does involve a difficult wafer bonding step.
To achieve high wafer bond yields, stringent cleanliness and planarization is required, which makes the fabrication of such integrated devices difficult and expensive.
Alternatively, active devices can be transfer printed or flip-chip bonded to the silicon nitride PIC. High quality SiN films are both CMOS compatible and offer high performance passive devices rivaling what can be achieved with silica PLC's but in much smaller die. III-V material offers high quality active photonic devices. The problem is to find a way to efficiently couple light between SiN waveguides and III-V waveguides, such as indium phosphide (InP). Ideally, to make the platform suitable for active devices, such as lasers, modulators and detectors, an optical coupling scheme which adiabatically transfers light between the different waveguides is preferred. However, it is difficult to transfer light from an III-V device directly to the SiN without extremely narrow tapers and/or vertical tapering. Consequently a silicon interlayer is often used.
In Sun et al, “Adiabaticity criterion and shortest adiabatic mode transformer in a coupled waveguide system”, OPTICS LETTERS, Vol. 34, No. 3, Feb. 1, 2009, the criteria that are required for adiabatic coupling are summarized. However the large refractive index difference between SiN and III-V material means that the taper on the III-V waveguide would need to be very narrow, for instance a width less that 100 nm, and/or very thin, for instance a thickness lower than 200 nm, to meet these criteria. Neither of these requirements is easy to achieve with processing techniques common in III-V wafer fabrication.
Therefore one barrier to integration of III-V actives to SiN passives is the difficulty in transferring light between the two waveguides due to the large refractive index contrast and consequently the need to define a very thin III-V tip, for instance smaller than 100 Nanometers. In Piels et al, “Low loss Silicon nitride AWG demultiplexer heterogeneously integrated with III-V photodetectors”, Journal of Lightwave Technology, Vol. 32, No. 4, Feb. 15, 2014, an alternative approach is described in which silicon as an intermediate layer is used. Although silicon has a refractive index comparable to III-V materials, it is easy to fabricate tapers which allow coupling to SiN. The silicon taper can be defined using CMOS fabrication techniques and the tolerances mentioned above are easily achievable, especially when using 192 Nanometers DUV (deep ultraviolet light) stepper technology and appropriate etch equipment. The taper required in the III-V waveguide to couple adiabatically to the silicon waveguide is well within the capability of most III-V fabrications, particularly if the silicon thickness is greater than 300 nm. A disadvantage of the approach described in this paper is that a wafer bonding step is required to add the mono-crystalline silicon layer above the planarized SiN layer. In this case the SiN is extremely thin, for instance in a range of 70 nm to 100 nm and this does make planarization easier. However, the planarization becomes much harder with thicker SiN waveguide layers, for instance with a thickness in the range of 300 nm to 400 nm.
In US 2009/016399 A1 an evanescent coupling of light from silicon waveguides to III-V photodetectors is described. Also in Roelkens et al, “Laser emission and photodetection in an InP/InGaAsP layer integrated on and coupled to a Silicon-on-Insulator waveguide circuit”, Optics Express, Vol. 14, No. 18, 2006 or in Fang et al, “1310 nm evanescent laser”, Optics Express, Vol. 15, No. 18, 2007 lasers, tunable lasers, modulators and detectors in III-V heterogeneously integrated on an SOI platform have been described. However this platform assumes silicon waveguides will be used for passive structures. There is no consideration how to achieve low loss or high performance passive devices.
A barrier to integration of III-V actives to silicon nitride passives is the difficulty in transferring light between the two waveguides due to the large refractive index contrast and the need to define a very narrow (<100 nm) wide III-V tip.
The limitation of using silicon waveguides to fabricate passive devices has been recognized for some time. In Doerr et al, “Eight-Channel SiO(2)/Si(3)N(4)/Si/Ge CWDM Receiver”, IEEE PHOTONICS TECHNOLOGY LETTERS, Vol. 23, No. 17, DOI: 10.1109/LPT.2011.2158091, published in Sep. 1, 2011 or in Chen et al, “Monolithically integrated 40-channel multiplexor and photodetector array on silicon”, IEEE photonics Technology Letters, Vol. 23, No. 13, 2011 a plasma-enhanced chemical vapor deposition (PECVD) SiN deposited on top of the silicon is used. This approach is gaining popularity at the OFC 2015, see for instance Huang et al, “Ultra-low loss CMOS compatible multi-layer Si3N4-on-SOI platform for 1310 nm Wavelength”, W4A.5 or Poon et al, “integrated photonic devices and circuits in hybrid silicon platforms”, Th3F.1. Thus, the SiN is integrated monolithically above the Silicon on insulator (SOI). The disadvantage of this approach is that the temperature budget for the silicon nitride processing is limited as the SOI active devices have already been formed. This means that the refractive index and uniformity control and absorption around 1520 nm is much worse than would be the case for a low pressure chemical vapor deposition (LPCVD) SiN waveguide.